1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit which uses a MOS device with non-lightly doped source and drain regions for protecting other MOS devices with lightly doped source and drain regions on an integrated circuit.
2. Description of the Prior Art
Integrated circuits (ICs) are susceptible to damage due to electrostatic discharge (ESD). An ESD event occurs whenever a packaged IC is subject to the dissipation of static electricity, which may occur whenever the pins of the IC come into contact with another surface. Thus, the likelihood of an ESD event damaging or destroying an IC is substantial during packaging and handling of the IC.
The human body is a major source of static charge. The human body can be modeled as a 100 pico-farad capacitor capable of storing 3.0 KV and having series resistance of 1.5K ohms. When the pins of the packaged IC are touched, a peak current equal to 3.0 KV/1.5K ohms=2 amps is passed through the MOS devices on the IC. With ICs having MOS devices with one micron or less geometries, discharges of 2 amps or less may damage or even destroy the gate oxides of the MOS devices on the IC if adequate ESD protection is not provided.
The consequences of ESD damage can be severe. The internal circuitry of the IC may be completely destroyed, rendering the device useless. More than half of the ICs returned by customers are due to ESD damage. Perhaps of even greater consequence, the ESD event may render the IC only partially inoperative. If undetected, the IC may be installed into a final product, where, after subsequent use, the damaged circuit may degenerate and eventually cause complete IC failure.
U.S. Pat. Nos. 4,829,350, 4,811,155, 4,855,620 and 4,692,834 all disclose ESD protection circuits in which the channel of an MOS device is coupled between ground and a pin of the IC. Such an MOS device has a parasitic bipolar transistor coupled in parallel with the MOS device. When a positive ESD event occurs at the pin, the bipolar transistor is forward-activated, and a substantial portion of the ESD current is passed through it to ground. Similarly, in the event of a negative ESD occurrence with respect to the pin or ground, the parasitic bipolar transistor is reverse-activated, and the ESD current is passed through it from ground to the pin.
State of the art CMOS devices currently have a channel width of approximately 0.8 microns. For one micron or smaller CMOS process flows, lightly doped regions are provided between the gate and the source and drain respectively for the N channel devices. The advantages of these lightly doped regions are set forth in Microelectronic Devices, Edward S. Yang, McGraw Hill, 1988, pp. 292-294.
Referring to FIG. 1, a cross section of an MOS device with lightly doped source and drain regions regions is shown. The MOS device fabricated on a substrate 12, includes a gate 14, a gate oxide 16, a channel 18, a highly doped (N+) source 20, a first lightly doped (N-) region 22, a highly doped (N+) drain 24, and a second lightly doped (N-) region 26. When the MOS device is turned on, a depletion region 28 is formed along the channel 18. It is well known that the source and drain regions of an MOS device are interchangeable, and therefore both the first and second lightly doped regions 22 and 26 are hereinafter referred to as lightly doped drain (LDD) regions.
It is important to note that in IC fabrication processes, one set of masks are used to create all the devices on an IC. Therefore, if MOS devices with LDD regions are used for circuit design, the other IC devices, such as those dedicated for ESD protection, are also MOS devices with LDD regions. Thus, current one micron or less CMOS ICs use similar ESD protection circuits as described in the aforementioned prior art patents, except the MOS devices of the prior art are replaced with MOS devices with LDD regions.
Referring to FIG. 2, a prior art ESD protection circuit using an MOS device with LDD regions is shown. The circuit includes the channel of the LDD MOS device 10 coupled between the pin 32 and ground. The LDD MOS device 10 is configured so that the source 20 and first lightly doped region 22 are coupled to pin 32, and the drain 24 and second lightly doped region 26 are coupled to ground. Capacitor (Cgs) represents the capacitance between the source and the gate, capacitor (Cgd) represents the capacitance between the drain and gate and R represents the gate to ground resistance.
A parasitic bipolar transistor 36 is also coupled between line 34 and ground. The emitter 37 of the bipolar transistor corresponds to the second (N-) region 26 and drain 24, the base corresponds to the channel 18, and the collector 39 corresponds to the first (N-) region 22 and the source 20. Since the source and drain regions of the MOS device are readily interchangeable, the emitter and the collector of the parasitic bipolar transistor 36 are also interchangeable.
In the event of a positive (with respect to ground) ESD with a magnitude (V) occurs at pin 32, the ESD induces the MOS transistor 10 and its parasitic bipolar transistor 36 to breakdown and to be biased into a conductive state. Both breakdown and the biasing actions of the transistors are responsible for dissipating the ESD.
If the voltage (V) is large enough, breakdown between the first and second (N-) LDD regions of MOS transistor 10 may occur, creating the depletion region 28 across the channel 18 of the MOS device. As a result, electrons are swept out of the channel 10 toward the pin 32, thereby dissipating the ESD event to ground. This phenomena can also be described in view of the parasitic bipolar transistor 36. If the ESD event at pin 32 is large enough, the PN diode between the (N-) emitter 37 and the P base breaks down. As a result, electrons in the emitter are swept across the base 38 and to the collector 39. Thus, the positive ESD is dissipated to ground.
It is believed a voltage of approximately (V/2) is simultaneously applied to the gate 14 of the LDD MOS device 10 through capacitor C1. The voltage applied to the gate turns on the MOS device which enhances the formation of the depletion region 28 across channel region 18, and thus compliments the flow of electrons from the second LDD region 24 across the depletion region from ground to the pin 32. This second phenomena can also be described in view of the parasitic bipolar transistor 36. The voltage (V/2) applied to the base 38 biases the bipolar transistor 36 into the forward active state. As a result, electrons are emitted from the emitter 37 and collected at the collector 39 coupled to pin 32. Thus the positive ESD is dissipated to ground.
Similarly, in the event of a negative ESD occurrence at the pin with respect to the pin or ground, a channel is again formed between the source and drain and the MOS device is turned on. With respect to parasitic bipolar transistor 36, the transistor is reverse-activated in a manner opposite that described above. As a result, the negative ESD is dissipated from ground to the pin.
Although for reasons not completely understood, it is believed the majority of the ESD is dissipated through the action of the parasitic bipolar device 36 rather than that of the MOS device 10. It is believed that because the MOS channel current is much smaller than the bipolar device, the majority of the ESD is dissipated through the action of the parasitic bipolar transistor 36.
For one micron or smaller devices, LDD MOS devices are not effective for ESD protection for several reasons. First, with the (N-) LDD regions 22 and 26, a larger voltage is required to induce breakdown than if an (N+) region was present in its place. Thus, the protection circuit maybe destroyed before being activated. Second, once the bipolar transistor 36 is turned on, the efficiency of the (N-) emitter (either region 22 or 26) of the parasitic bipolar transistor 36 is much lower than that of a similarly configured bipolar device with an (N+) emitter. Once activated, the number of electrons that can be emitted from the (N-) emitter is significantly smaller, thereby reducing the amount of ESD induced current it can handle.
In summary, the combination of the very thin gate oxides used in one micron or smaller CMOS devices as well as the lack of adequate ESD protection, renders such integrated circuits highly susceptible to ESD induced damage or destruction.